Design and FPGA implementation of forward error corrector for digital transreceiver

Citation metadata

Authors: Nitin S. Sonar and A.D. Shaligram
Date: Aug. 1, 2009
From: International Journal of Applied Engineering Research(Vol. 4, Issue 8.)
Publisher: Research India Publications
Document Type: Report
Length: 1,414 words
Abstract :

The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital communication channels. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. This paper presents a Viterbi Decoder (VD) architecture for correcting data errors in data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This viterbi Decoder has been conceived as a building block of error correcting system for wireless transmission of data. To improve the limited capacity of the communication channels, it has been widely deployed in many wireless communication systems. The Viterbi algorithm is the most extensively employed decoding algorithm for convolutional codes. In this paper we present a Field Programmable Gate Array implementation of Viterbi Decoder with a constraint length of 3 and a code rate of both 1/2 and 1/3. The chosen architecture implements the Trace Back Algorithm (TBA). The architecture has been tested and verified with a Xilinx SPARTAN-3E FPGA, to provide a generalized co-simulaton/co-design testbed. Keywords: Convolutional Codes, Viterbi decoding, Field Programmable Gate Array (FPGA) implementation.

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Source Citation

Source Citation   (MLA 8th Edition)
Sonar, Nitin S., and A.D. Shaligram. "Design and FPGA implementation of forward error corrector for digital transreceiver." International Journal of Applied Engineering Research, vol. 4, no. 8, 2009, p. 1591+. Gale Academic Onefile, Accessed 21 Sept. 2019.

Gale Document Number: GALE|A215514761