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    Academic Journals

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• XOR-FREE implementation of convolutional encoder for reconfigurable hardware

  Authors:Gaurav Purohit, Kota Solomon Raju, and Vinod Kumar ChaubeyFrom:International Journal of Reconfigurable ComputingPeer-Reviewed

  Annual 20163,847 words Report 1440LThis paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator...

• Design Considerations When Accelerating an FPGA-Based Digital Microphone Array for Sound-Source Localization

  Authors:Bruno da Silva, An Braeken, Kris Steenhaut, and Abdellah TouhafiFrom:Journal of Sensors (Vol. 2017) Peer-Reviewed

  Annual 201710,093 words Article 1300LThe use of microphone arrays for sound-source localization is a well-researched topic. The response of such sensor arrays is dependent on the quantity of microphones operating on the array. A higher number of...

• An efficient low power log based FPU design for FPGAs

  Authors:D. Vaithiyanathan and R. SeshasayananFrom:Advances in Natural and Applied Sciences (Vol. 9, Issue 6 SE) Peer-Reviewed

  June 20153,929 words Report 1730LAll new technical developments generally arise with complex problems demanding numerals that have more credence than normal integers this offer a great importance to the real valued floating point numbers. Though the...

• An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications

  Authors:Taha Beyrouthy and Laurent FesquetFrom:International Journal of Reconfigurable ComputingPeer-Reviewed

  Annual 20136,775 words Article 1250LThis paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement--on a full-custom asynchronous FPGA--secured functions that need to be robust against side-channel...

• Optimal partial reconfiguration for permanent fault recovery on SRAM-based FPGAs in space mission

  Authors:Jie Zhang, Yong Guan, and Chunjing MaoFrom:Advances in Mechanical EngineeringPeer-Reviewed

  Annual 20134,484 words Report 1330LIn this paper, we present a technique to maximize the lifetime of SRAM-based FPGAs in space mission. We focus on recovering permanent faults induced by SEE (single-events effect). In our technique, we use a fix-sized...

• Design of an asynchronous processor with bundled-data implementation on a commercial Field Programmable Gate Array.

  Authors:Jukiya Furushima, Masamitsu Nakajima, and Hiroshi SaitoFrom:Informatica (Vol. 40, Issue 4) Peer-Reviewed

  Dec. 20165,789 words Report 1340LIn this paper, we propose a modeling method and a design now to design asynchronous processors with bundled-data implementation on commercial Field Programmable Gate Arrays (FPGAs). The modeling method mainly concerns...

• Real time process monitoring and fault detection using linear array sensor with FPGA for textile industries

  Authors:S. Sajitha and M. JayasheelaFrom:Advances in Natural and Applied Sciences (Vol. 10, Issue 10 SE) Peer-Reviewed

  June 30, 20161,894 words Report 1090LCotton is naturally harvested and plays an important role in the production of fabrics. The presence of contamination makes it useless for fabric production. It is very tricky to maintain the quality of the cotton among...

• FPGA Implementation of Image Compression Algorithm Using Bottom-up Approach of Quad Tree Technique

  Authors:Satish Shah, Rakesh Soni, and Brijesh ShahFrom:IETE Journal of Research (Vol. 57, Issue 2) Peer-Reviewed

  March-April 20113,529 words Report 1270LByline: Satish. Shah, Rakesh. Soni, Brijesh. Shah This paper presents an optimal technique for image compression by which one can achieve maximal storage and transmission capabilities. Realizing image compression...

• FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

  Authors:Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, and Predrag SpasojevicFrom:International Journal of Reconfigurable Computing (Vol. 2017) Peer-Reviewed

  Annual 201711,901 words Article 1460LWe propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the...

• A project-based strategy for teaching robotics using NI's embedded-FPGA platform

  Authors:Muhammad Mysorewala and Lahouari ChededFrom:International Journal of Electrical Engineering Education (Vol. 50, Issue 2) Peer-Reviewed

  Apr. 20135,956 words Article 1710LThis paper discusses our project-based teaching and learning approach to infuse robotics education into our Control and Instrumentation programme at the KFUPM university. In the last two years, various practical...

• Hardware architecture for real-time computation of image component feature descriptors on a FPGA

  Authors:Abdul Waheed Malik, Benny Thornberg, Muhammad Imran, and Najeem LawalFrom:International Journal of Distributed Sensor Networks (Vol. 2014) Peer-Reviewed

  Annual 20148,968 words Report 1400LThis paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image...

• FPGA Realization and Lyapunov-Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks.

  Authors:J. Perez-Padron, C. Posadas-Castillo, J. Paz-Perez, E. Zambrano-Serrano, and M. A. Platas-GarzaFrom:Mathematical Problems in Engineering (Vol. 2021) Peer-Reviewed

  Sept. 23, 20218,033 words Article 1300LIn this paper, the trajectory tracking control and the field programmable gate array (FPGA) implementation between a recurrent neural network with time delay and a chaotic system are presented. The tracking error is...

• A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System.

  Authors:Peter Jamieson, Donald Blank, Janelle Ghanem, Tyler McGrew, and Giancarlo CortiFrom:International Journal of Reconfigurable Computing (Vol. 2022) Peer-Reviewed

  May 6, 20226,348 words Article 1430LIn this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array...

• FPGA-based real-time moving target detection system for Unmanned Aerial Vehicle application

  Authors:Jia Wei Tang, Nasir Shaikh-Husin, Usman Ullah Sheikh, and M.N. MarsonoFrom:International Journal of Reconfigurable ComputingPeer-Reviewed

  Annual 20168,730 words Report 1520LMoving target detection is the most common task for Unmanned Aerial Vehicle (UAV) to find and track object of interest from a bird's eye view in mobile aerial surveillance for civilian applications such as search and...

• A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

  Authors:Lorenzo Verdoscia and Roberto GiorgiFrom:Mathematical Problems in EngineeringPeer-Reviewed

  Annual 201613,323 words Article 1450LWe present a new type of soft-core processor called the "Data-Flow Soft-Core" that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on...

• Energy detector implementaton in FPGA for estimation of word boundaries/Energijos detektoriaus, naudojamo zodzio riboms nustatyti, igyvendinimas lauku programuojama logine matrica

  Authors:Liudas Stasionis and Tomyslav SledevicFrom:Science - Future of Lithuania (Vol. 5, Issue 2) Peer-Reviewed

  Apr. 20131,768 words Report 1200LThis paper describes implementation of the word boundary estimation module in FPGA. The boundary estimation module is based on energy detector. This module is optimized for implementation in FPGA. It occupies 54 logical...

• FPGA architecture, challenges and application: survey

  Author:Mallikarjun SarsambaFrom:Indian Journal of Scientific ResearchPeer-Reviewed

  Nov. 20152,656 words Report 1420LField-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A necessary part of their creation lies in their architecture, which governs the nature of...

• A scalable unsegmented multiport memory for FPGA-based systems

  Authors:Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, and Joseph ZambrenoFrom:International Journal of Reconfigurable ComputingPeer-Reviewed

  Annual 20155,629 words Report 1250LOn-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating...

• Efficient FPGA hardware reuse in a multiplierless decimation chain

  Authors:Guillermo A. Jaquenod, Javier Valls, and Javier SimanFrom:International Journal of Reconfigurable ComputingPeer-Reviewed

  Annual 20143,192 words Article 1570LIn digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the...

• System architecture for real-time face detection on analog video camera

  Authors:Mooseop Kim, Deokgyu Lee, and Ki-Young KimFrom:International Journal of Distributed Sensor Networks (Vol. 2015) Peer-Reviewed

  Annual 20157,469 words Report 1390LThis paper proposes a novel hardware architecture for real-time face detection, which is efficient and suitable for embedded systems. The proposed architecture is based on AdaBoost learning algorithm with Haar-like...